Memory Layout Engineer

Company Description F. Robin Technologies is the technology flagship of the F. Robin Group, delivering integrated solutions that connect PCB design, electronics manufacturing services (EMS), and strategic workforce deployment. Backed by an industrial ecosystem spanning energy, infrastructure, and packaging, the organization supports complex engineering and manufacturing projects with the resources of a diversified conglomerate and over 2,500 professionals. Core capabilities include high-density PCB layout, multi-layer board design, semiconductor R&D support, and end-to-end electronics production from prototyping to volume assembly. The company also provides scalable talent solutions across engineering, IT, and industrial sectors, enabling clients to address evolving workforce needs. F. Robin Technologies operates from its corporate headquarters at KOSMO ONE, Ambattur Industrial Estate, Chennai, Tamil Nadu, with project sites across key technology hubs.
Role Description The Memory Layout Engineer role is a full-time, on-site position based in Bengaluru South. The engineer will be responsible for creating, optimizing, and validating memory circuit layouts, ensuring adherence to design rules, performance targets, and reliability requirements. Day-to-day activities include collaborating with circuit design teams, performing layout-versus-schematic (LVS) and design rule checks (DRC), and refining layouts for area, power, and yield. The role involves close coordination with fabrication and packaging teams to support Design for Manufacturing (DFM) and Design for Test (DFT) considerations. The engineer will document layout methodologies, contribute to internal design standards, and support continuous improvement of memory design workflows and tool usage.
Qualifications
Strong proficiency in memory circuit layout, including SRAM, DRAM, or non-volatile memory structures, with experience in high-density layouts and multi-layer designs.
Hands-on experience with industry-standard EDA tools (e.g., Cadence, Synopsys, Mentor/Siemens) for layout creation, LVS, DRC, and parasitic extraction.
Solid understanding of semiconductor device physics, process technologies (CMOS, FinFET), and Design for Manufacturing (DFM) and Design for Test (DFT) principles.
Ability to interpret and apply foundry process design kits (PDKs), design rules, and reliability guidelines (EM, IR-drop, ESD).
Strong analytical and problem-solving skills, with attention to detail and ability to troubleshoot layout, mismatch, and convergence issues.
Effective communication and collaboration skills for working with cross-functional teams in design, verification, manufacturing, and packaging.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, VLSI, or a related discipline, or equivalent practical experience.
Prior experience in memory design, custom layout, or physical design in an ASIC/semiconductor environment is highly beneficial.

Work arrangement
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