Memory Layout Engineer

Company Description InSemi Technology Services Pvt. Ltd., founded in 2013, specializes in VLSI design services, embedded product development, and building strong links between academia and industry. The company’s core strengths include foundation IP for memory compilers and custom memories, analog, IO, and standard cells, as well as ASIC design and verification services. InSemi also provides technology and infrastructure solutions such as CAD, PDK, and techfile development and QA. Its embedded systems team covers end-to-end IoT product development, PCB schematic capture, layout design, product analysis, and embedded software and app development. The organization promotes a culture of technical excellence and innovation driven by a dynamic and forward-looking management team.
Role Description This is a full-time, on-site Memory Layout Engineer role based in Bengaluru South. The Memory Layout Engineer will be responsible for creating, optimizing, and validating custom memory layouts, ensuring that designs meet performance, power, area, and reliability requirements. Day-to-day work includes interpreting circuit schematics, developing transistor-level layouts, ensuring DRC/LVS compliance, and collaborating with circuit design, verification, and CAD teams. The role involves working closely with technology files and process design kits (PDKs), running layout verification, and contributing to layout quality improvements and best practices. The engineer will also support silicon debug, assist in yield and reliability improvement activities, and participate in continuous enhancement of layout methodologies and automation.
Qualifications
Strong experience in memory layout design, including custom SRAM, ROM, or register file layouts, with solid understanding of transistor-level design and floorplanning.
Proficiency with industry-standard layout and verification tools (e.g., Cadence Virtuoso, Synopsys, Mentor/Siemens tools) and familiarity with DRC, LVS, ERC, and parasitic extraction flows.
Knowledge of CMOS processes, PDK usage, design rules, and layout techniques for performance, power, area, and reliability optimization (e.g., matching, shielding, IR drop, EM).
Background in VLSI design fundamentals, including digital and analog design concepts relevant to memory, and basic understanding of timing, noise, and signal integrity.
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or a related field, or equivalent practical experience.
Ability to collaborate effectively with cross-functional teams, communicate clearly, and document design decisions and layout guidelines.
Attention to detail, strong analytical and problem-solving skills, and a willingness to learn and adapt to evolving technologies and flows.
Prior experience in ASIC design services, foundation IP, or memory compiler environments is a plus; exposure to scripting (e.g., SK

Work arrangement
No