Live opening · Posted 5 days ago

Senior Physical Design Engineer

Insemi Technology Services Pvt. Ltd. · Bengaluru South, Karnataka, India (On-site)
Linkedin No
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At a glance

The key details from the original listing.

Posted 5 days ago
CompanyInsemi Technology Services Pvt. Ltd.
LocationBengaluru South, Karnataka, India (On-site)
Work modeNo
SourceLinkedin
Listed5 days ago

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About the role

Description supplied by the original job listing.

Company Description Insemi Technology Services Pvt. Ltd., founded in 2013, specializes in VLSI design services, embedded product development, and fostering collaboration between academia and industry. The company’s core focus since 2016 has been engineering design services in chip design and embedded domains, offering expertise across Foundation IP, ASIC design and verification, and CAD/PDK infrastructure. Insemi’s embedded systems team delivers end-to-end product development for IoT solutions, including PCB design, product analysis, and embedded software and app development. The organization promotes a culture of technical excellence, innovation, and continuous learning, supported by a dynamic and young leadership team.
Role Description The Senior Physical Design Engineer will work on complex ASIC and SoC projects, taking ownership of physical implementation from RTL to GDSII. Day-to-day responsibilities include floorplanning, power planning, place-and-route, timing closure, and integration with physical verification flows, collaborating closely with RTL, logic, and circuit design teams. The role involves analyzing design constraints, optimizing for power, performance, and area, performing ECOs, and driving sign-off across STA, DRC, LVS, and IR/EM checks. The engineer will mentor junior team members, contribute to methodology improvements, and support cross-functional reviews and tape-out activities. This is a full-time, on-site role based in Bengaluru South.
Qualifications
Strong expertise in Physical Design, including floorplanning, power planning, place-and-route, and timing closure.
Hands-on experience in Physical Verification, covering DRC, LVS, and reliability checks (IR drop, EM).
Solid understanding of Logic Design and Circuit Design concepts for digital ASIC/SoC implementations.
Proficiency in RTL Design fundamentals, constraints definition, and interaction with front-end teams.
Experience with industry-standard EDA tools (e.g., Cadence, Synopsys, Mentor) and scripting (Python, Perl, Tcl, or Shell).
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or a related discipline.
Proven background in advanced process nodes, multi-clock designs, and low-power methodologies.
Strong analytical, problem-solving, and communication skills, with the ability to work effectively in collaborative engineering teams.
Prior experience mentoring engineers and contributing to physical design methodologies is highly beneficial.

Work arrangement
No

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