Live opening · Posted 5 days ago

Physical Design Lead (Full Chip)

7Rays Semiconductors · Greater Hyderabad Area (Hybrid)
Linkedin Hybrid
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At a glance

The key details from the original listing.

Posted 5 days ago
Company7Rays Semiconductors
LocationGreater Hyderabad Area (Hybrid)
Work modeHybrid
SourceLinkedin
Listed5 days ago

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About the role

Description supplied by the original job listing.

At 7Rays Semiconductors (https://7rayssemi.com/), we provide end-to-end VLSI design solutions to help our clients achieve execution excellence. Our team of experts specializes in architecture, RTL design, verification, validation, physical design, implementation, and post-silicon validation using the latest technologies and methodologies
We work closely with our clients, building effective partnerships to deliver high-quality solutions tailored to their needs. With a proven track record of successful projects, we are committed to excellence and innovation in semiconductor design.
Job: Senior Physical Design Engineer
Experience: 7–12+ years
Location: Hyderabad
7+ years experience in Physical Design
Extensive expertise in Floorplanning for SoC using Innovus
Must have a knowledge and implementation strategies to create an IO ring in accordance design specification
Have a deep knowledge on ESD, latch-up etc for foundary requirements and placement strategies
Should have a higherarchial design implementation knowledge which include partitions/HMs/tiles push down to each core/tile
PG creation and push down methodologies knowledge and implementation
Should have a knowledge on Analog components and their requirements in placements according to design specifications
RDL knowledge and working with packaging is a must for SoC floorplan designer
PV clean-up on floorplan and self derive in all the sign-off including Physical Verification, ESD and foundry/Analog requirements
Deep scripting knowledge is essential
Should be capable of providing solutions to flow, tool, design setup elated issues proactively at large team level
Strong TCL/Perl/Makefile scripting knowledge as well as experience developing complex algorithms, managing, and regressing P&R flows.
Familiar with sign-off issues (metal-fill, spare-cells, DFM rules, boundary-cells, etc.) for the latest generations of process technologies
Good problem-solving capabilities, proactive, hardworking with strong interpersonal skills
Bachelors Degree in Electrical, Electronics or Computer Engineering

Work arrangement
Hybrid

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