Live opening · Posted 5 days ago

Design Verification Engineer

KPTA Systems · Bengaluru, Karnataka, India (Hybrid)
Linkedin Hybrid
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At a glance

The key details from the original listing.

Posted 5 days ago
CompanyKPTA Systems
LocationBengaluru, Karnataka, India (Hybrid)
Work modeHybrid
SourceLinkedin
Listed5 days ago

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About the role

Description supplied by the original job listing.

Company Description KPTA Systems is a semiconductor services company founded by experienced engineers specializing in ASIC and FPGA design and verification. The name KPTA reflects a commitment to advancing knowledge through technology and time, and to transforming the world through innovation. The team focuses on delivering high-quality, secure, and timely RTL design and functional verification solutions starting from scratch-level concepts. KPTA Systems is recognized in the industry for its strong technical expertise and dedication to robust engineering practices, offering an environment where professionals can work on complex verification challenges and grow their skills.
Role Description The Design Verification Engineer will work as part of a cross-functional team in Bengaluru, in a full-time hybrid role that combines on-site collaboration with some work-from-home flexibility. Day-to-day responsibilities include developing and executing verification plans, creating testbenches, writing test cases, and performing functional and formal verification of complex digital designs. The role involves close collaboration with RTL design engineers to review specifications, identify corner cases, and ensure thorough coverage of design features. The engineer will debug failing tests, analyze root causes, and work with the team to implement fixes and improvements. Additional tasks include maintaining verification environments, documenting methodologies and results, and contributing to continuous improvements in verification flows and tools.
Qualifications
Candidates should possess strong skills in RTL Design and a solid understanding of Computer Architecture.
Candidates should possess hands-on expertise in Functional Verification, including testbench development and coverage analysis.
Candidates should possess experience in Formal Verification methodologies and tools.
Candidates should possess strong Debugging skills for complex digital logic and verification environments.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
Proficiency with hardware description and verification languages (such as Verilog, SystemVerilog, VHDL, UVM) and industry-standard EDA tools.
Strong analytical thinking, attention to detail, and the ability to collaborate effectively in a team-based environment.
Experience in ASIC/FPGA design flows and semiconductor industry projects is highly beneficial.
Experience Level 3-5 years

Work arrangement
Hybrid

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