Application Engineering, Principal Engineer

We Are
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are
You are a DDR/LPDDR Controller System Architecture Specialist who can work directly with customer architects to close real system-level memory subsystem design decisions.
You are comfortable discussing SoC integration, memory subsystem architecture, controller configuration, performance optimization, power management, validation, and interoperability topics. You can help customers evaluate technical trade-offs and guide them toward practical architecture decisions.
This is a customer-facing technical role. You will help customers integrate DDR/LPDDR controller IP into complex SoCs, identify key requirements or gaps, and translate customer feedback into actionable input for Synopsys Product Management, R&D, and roadmap planning.
What You’ll Be Doing
Own the technical architecture engagement for DDR/LPDDR controller IP with strategic customers, from early platform requirements through architecture closure and initial deployment readiness.
Work with customer architects and engineering teams to define suitable DDR/LPDDR memory subsystem configurations for advanced SoC platforms.
Analyze system-level trade-offs related to memory bandwidth, latency, power efficiency, quality of service, reliability, validation, and scalability.
Translate customer platform requirements and integration constraints into clear feedback for Synopsys Product Management, R&D, and roadmap planning.
Support technical closure of design wins by providing architecture guidance, configuration recommendations and competitive positioning.
Develop reusable technical material, application notes, and customer-facing guidance based on real engagement experience.
Train FAEs and customer teams on DDR/LPDDR architecture, memory subsystem integration, performance tuning, validation expectations, and deployment best practices.
The Impact You Will Have
Improve the quality of DDR/LPDDR design wins by ensuring customer memory architectures are technically sound before commitment.
Strengthen Synopsys DDR/LPDDR roadmap by feeding real customer memory subsystem requirements into product planning and R&D execution.
Reduce customer integration risk by identifying architecture, performance, power, validation, and bring-up issues early.
Help establish Synopsys as a trusted technical partner for next-generation AI, HPC, mobile, automotive, networking, and edge computing platforms.
What You’ll Need
Bachelors and/or Masters Degree in Electrical and/or Electronic Engineering, Computer Engineering or Computer Science
5+ years of experience in DDR/LPDDR architecture, memory subsystem design, SoC integration, silicon validation, systems engineering, applications engineering, or customer-facing technical leadership.
Solid understanding of DDR and/or LPDDR controller IP, including memory architecture concepts, controller configuration, scheduling, quality of service, power management, training, validation, or system integration.
Good system-level understanding of SoC integration and ability to reason through memory bandwidth, latency, power efficiency, quality of service, reliability, validation, and software/firmware trade-offs.
Experience engaging directly with customer architects, design teams, validation teams, and technical decision-makers.
Ability to translate ambiguous customer requirements into clear technical recommendations, product feedback, and closure plans.
Strong technical communication skills, including clear written analysis, structured trade-off explanation, and ability to align customer, sales, product, and engineering teams.
Nice to Have
Experience with Linux, firmware bring-up, or software-driven debug of DDR/LPDDR subsystems.
Familiarity with advanced SoC architectures used in AI, HPC, automotive, mobile, networking, or compute platforms.
Experience with memory performance analysis, traffic modeling, quality-of-service management, memory hierarchy optimization, or system-level benchmarking.
Knowledge of advanced topics such as DDR5, LPDDR5X, LPDDR6, memory training algorithms, RAS features, chiplet-based memory architectures, or AI memory bandwidth optimization.
The Team You’ll be a Part Of
You will be part of our IP high-performance computing applications engineering team, a group of dedicated professionals who are passionate about technology and innovation. The team focuses on helping customers integrate more capabilities into SoCs faster, working collaboratively across geographic and organizational boundaries to drive revenue growth and accelerate business closure.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
Inclusion and Diversity
Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Work arrangement
No