R&D Engineering, Sr Engineer

Alternate Job Titles
Standard Cell Library Characterization Engineer
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent enough time in library characterization to know that a Liberty model is only as good as the corner cases you tested and the correlations you actually validated. You understand that when a designer's STA run fails because of a timing model mismatch, it is not just a data issue, it is hours of someone's schedule gone, and you take that seriously.
You are comfortable moving between SPICE simulations, Liberty file generation, and debugging why a CCS noise model behaves differently than expected across PVT corners. When a correlation gap shows up between characterization and static timing analysis, you do not just log it, you dig in, reproduce it, and figure out what assumption broke down.
You know the difference between running a characterization flow and owning it. Running it means you execute scripts. Owning it means you catch the issue before QA does, you spot the pattern in regression failures, and you know when a model needs another pass even if it technically meets spec.
At Synopsys, you will work on standard cell libraries that power advanced node designs across the semiconductor industry. The libraries you characterize will be used in real tapeouts, and the quality bar is not negotiable.
What You'll Be Doing
Characterize and model standard cell libraries for advanced technology nodes, generating Liberty files including NLDM, NLPM, CCS timing, CCS noise, ECSM, LVF, AOCV, POCV, spatial OCV, aging, and EM models
Handle characterization across a wide range of cell types: combinational, sequential, clock gating, synchronizers, retention, level shifters, power gating, always-on, filler, and decap cells
Debug and resolve correlation issues between characterization results, static timing analysis, and SPICE simulations, working across tool flows to identify root causes
Execute QA checks, regression analysis, and release validation to ensure library deliverables meet quality and accuracy standards before they ship
Drive methodology improvements and automation initiatives that make characterization flows faster, more reliable, and easier to maintain across multiple projects
Coordinate project execution timelines, manage deliverables, and communicate status across cross-functional teams including design, verification, and product engineering
Support library releases by validating models against design rule checks, performing sanity testing, and ensuring documentation is complete and accurate
The Impact You Will Have
Enable accurate timing closure for advanced node designs by delivering high-quality Liberty models that designers and STA tools depend on
Reduce correlation gaps between characterization and silicon behavior, improving predictability and reducing costly respins for customers
Accelerate library development cycles by building automation and improving characterization flows that scale across multiple technology nodes
Increase library quality and reliability through rigorous QA, regression testing, and validation processes that catch issues before release
Support successful tapeouts by ensuring standard cell libraries meet performance, power, and area targets across all operating conditions
Contribute to methodology evolution by identifying gaps, proposing solutions, and implementing improvements that benefit the entire characterization team
Help Synopsys maintain its leadership in library IP by delivering models that meet the precision and robustness requirements of cutting-edge semiconductor designs
What You'll Need
Bachelor's or Master's degree in Electronics, VLSI, Microelectronics, or a related technical field
2+ years of hands-on experience in standard cell library characterization and Liberty modeling
Strong understanding of Liberty file formats including NLDM, CCS, ECSM, and advanced modeling constructs like AOCV, POCV, and aging models
Experience characterizing multiple cell types: combinational, sequential, clock gating, level shifters, retention, or power management cells
Solid grasp of SPICE simulation, timing analysis concepts, and correlation methodologies between characterization tools and STA flows
Proficiency in scripting languages like Python, Tcl, or Perl for automation, data analysis, and flow development
Experience with industry-standard characterization tools and STA platforms is a strong plus
Who You Are
You can look at a Liberty file and spot when a timing arc does not make sense or a capacitance value looks off, and you know how to trace it back to the characterization setup
When a correlation issue appears, you do not wait for someone else to debug it, you pull the SPICE deck, compare waveforms, and figure out where the model diverged
You are organized enough to manage multiple library releases in parallel without losing track of which models are validated, which are in QA, and which need another pass
You can explain a complex characterization issue to a design engineer or a project lead in a way that makes sense without dumbing it down or losing the technical detail
You push back when a release timeline does not leave enough room for proper validation, because you know that shipping a bad model costs more than delaying a release by a few days
You treat automation as part of the job, not extra credit, and you are always looking for repetitive tasks that should be scripted instead of done manually
The Team You'll Be Part Of
You will join the Library Characterization team at Synopsys, a group responsible for characterization, validation, QA, release management, and methodology support for advanced standard cell libraries across multiple technology nodes. Your recruiter will share more about the team structure, current projects, and how the team collaborates with design, product engineering, and customer-facing groups during the interview process.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Work arrangement
No