Senior Staff Analog Layout Engineer

We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent the better part of a decade building analog layouts that do not just pass verification, they perform in real silicon under real conditions. High-speed differential pairs, micro bump planning, die-to-die interconnects, these are not abstract concepts to you, they are problems you have solved repeatedly and refined over time. You know that a transmitter layout that looks clean in Virtuoso can still fail at the package if you did not think three steps ahead about return paths, skew, and substrate coupling.
You do not treat floor planning as a one-time exercise. You iterate with circuit designers, package engineers, and digital integration teams because you have learned that the best layouts emerge from collaboration, not isolation. When an EM/IR check flags a violation two days before tape out, you do not panic, you debug, you fix, and you close it.
You have worked on chiplet architectures, 2.5D integration, or advanced packaging, and you understand that UCIe is not just another interface, it is a shift in how we think about die boundaries, signal integrity, and physical partitioning. At Synopsys, you will work on IP that defines how chiplets talk to each other, and the layouts you create will ship in products that matter.
What You'll Be Doing
Design and deliver full-custom analog layouts for UCIe PHY blocks including transmitters, receivers, drivers, equalizers, DLLs, bias circuits, calibration engines, and regulators
Execute PHYTOP-level floor planning, bump planning, micro bump architecture, and channel routing with package co-design considerations for 2.5D/3D integration
Implement high-speed differential routing with precise length matching, skew control, shielding, symmetry, and signal integrity optimization across die and package boundaries
Drive physical verification closure including DRC, LVS, ERC, antenna checks, density rules, LPE extraction, EM/IR analysis, and reliability signoff
Collaborate with ASIC physical design teams to integrate analog layouts into top-level flows, generate LEFs, support place-and-route, and resolve integration issues
Develop layout methodologies, automation scripts, and reusable design flows that improve efficiency and consistency across the team
Lead technical reviews, mentor layout engineers, resolve complex cross-domain issues, and drive tape out execution with global circuit design, package, and reliability teams
The Impact You Will Have
Your layouts will enable UCIe die-to-die interfaces that ship in chiplet-based products across the semiconductor industry
The floor plans and bump architectures you create will define how analog PHYs integrate with digital logic, package substrates, and interposers in advanced 2.5D/3D systems
Your signal integrity work will directly affect whether high-speed channels meet performance targets in real silicon, not just simulation
The verification methodologies and automation you build will accelerate tape out cycles and reduce respins for future PHY designs
Your collaboration with package and digital teams will resolve integration challenges that would otherwise delay or compromise product quality
The engineers you mentor will carry forward the layout practices and problem-solving approaches you establish
Your contributions will help Synopsys deliver industry-leading UCIe IP that powers the next generation of chiplet ecosystems
What You'll Need
Diploma or Bachelor's degree in Electrical Engineering, Electronics Engineering, or related technical field
8 to 15 years of hands-on experience in analog or mixed-signal custom IC layout design
Proven track record designing layouts for UCIe PHY, high-speed SerDes, or die-to-die interface IP with successful tape outs
Deep expertise in micro bump planning, bump map architecture, package-aware floor planning, and die/package co-design for 2.5D/3D integration including interposers, RDL, and TSVs
Strong command of high-speed differential routing techniques including length matching, skew control, shielding, symmetry, and signal integrity-driven layout practices
Demonstrated experience closing DRC, LVS, ERC, EM/IR, antenna, density, and reliability checks through tape out on advanced process nodes
Experience integrating analog layouts with ASIC physical design flows, LEF generation, and top-level verification is a strong plus
Who You Are
You can walk into a floor planning meeting with incomplete specs, ask the right questions about power distribution and signal flow, and walk out with a layout strategy that works
When a package engineer tells you the micro bump pitch changed, you do not just update the layout, you think through the implications for channel routing, return paths, and crosstalk
You have debugged an LVS mismatch at 2 a.m. before tape out and found it was a subtle device matching issue that three other people missed
You can explain to a circuit designer why their ideal placement will not work given EM constraints, and propose an alternative that meets both performance and reliability requirements
You keep track of five parallel layout blocks, their verification status, and their integration dependencies without losing sight of the tape out timeline
You document your work clearly enough that an engineer in a different time zone can pick up your layout, understand the intent, and continue without a handoff call
The Team You'll Be Part Of
Your recruiter will share more about the team structure and mission during the interview process.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Work arrangement
No