Sr staff STA engineer

Company Description Mythic is a pioneering AI hardware company built on analog compute-in-memory technology, an architecture that processes data where it resides to drastically reduce energy use and increase efficiency. Originating from University of Michigan research, Mythic’s platform delivers up to 100x efficiency gains for AI inference at scale, serving data center, automotive, robotics, and defense applications. The company is focused on challenging the GPU status quo with a 1,024-chiplet architecture designed for the largest LLM workloads in the data center. Supported by an oversubscribed $125M funding round from leading investors such as Honda, Lockheed Martin, SoftBank, and DCVC, Mythic offers opportunities to work on cutting-edge AI hardware and systems. Team members collaborate across disciplines to build high-impact solutions for customers who demand performance without unsustainable energy costs.
Role Description The Sr Staff STA Engineer is responsible for leading static timing analysis for complex SoC and chiplet-based designs, ensuring timing closure across multiple process, voltage, and temperature corners. This full-time hybrid role is based in Bengaluru, with a mix of on-site collaboration and flexibility for some work from home. Day-to-day responsibilities include developing and maintaining timing constraints, running and analyzing STA using industry-standard tools, and partnering with RTL, synthesis, and physical design teams to identify and resolve timing bottlenecks. The role also involves defining timing methodologies and flows, driving automation and scripting for STA tasks, and mentoring junior engineers on best practices. The Sr Staff STA Engineer will collaborate closely with architecture and verification teams to align timing requirements with performance, power, and area targets for Mythic’s AI inference hardware.
Qualifications
Expertise in static timing analysis, timing sign-off, and timing closure for complex digital designs using industry tools (e.g., PrimeTime or equivalent).
Strong background in digital design concepts, including RTL design, synthesis, clock tree design, and understanding of physical design impacts on timing.
Proficiency in scripting and automation (e.g., Python, Tcl, Shell) to build efficient STA flows and reports.
Experience with advanced process nodes, multi-clock and multi-voltage domains, and handling on-chip variability and signal integrity considerations.
Ability to collaborate effectively with cross-functional teams (architecture, RTL, PD, verification) and provide clear guidance on timing-related trade-offs.
Demonstrated experience in leading complex projects, mentoring engineers, and establishing timing methodologies in a high-performance hardware environment.
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field; extensive relevant industry experience in STA and digital hardware design.
Experience with high-performance compute or AI accelerator

Work arrangement
Hybrid