Analog Layout Engineers - Lead

Company Description SiMaxTech Pvt Ltd is a fast-growing semiconductor design services company that delivers end-to-end chip solutions to global customers. The company combines deep expertise across the semiconductor value chain with strong capabilities in analog circuit design, RTL design, design verification, custom layout, physical design, and embedded design. SiMaxTech works across a wide range of process technologies, from mature nodes such as 65nm, 40nm, and 28nm to advanced nodes including 7nm, 5nm, 3nm, and emerging nodes like 2nm and 18A. Guided by a vision to be the preferred semiconductor design partner worldwide, the organization focuses on continuous learning, innovation, and execution excellence. Team members join a customer-centric environment that emphasizes performance, reliability, scalability, and high-quality design solutions across the full chip development lifecycle.
Role Description This is a full-time, on-site Analog Layout Engineers – Lead role based in Bengaluru South. The lead engineer will be responsible for driving analog and mixed-signal layout design from concept to tape-out, collaborating closely with circuit design teams to translate schematics into optimized layouts that meet performance, reliability, and manufacturability requirements. Day-to-day responsibilities include creating and reviewing layout floorplans, performing transistor-level and block-level layout, optimizing matching, parasitics, and routing, and ensuring adherence to design rules, layout best practices, and project schedules. The role also involves coordinating physical verification activities, resolving DRC/LVS and other sign-off issues, mentoring junior layout engineers, and contributing to layout methodologies and design flows. The engineer will interact with cross-functional teams across front-end and back-end domains to support successful delivery of full-chip and SoC projects.
Lead Analog Layout Engineers,
Experience: 6 -9 Years
Location: Bangalore
Qualifications
Strong proficiency in layout-focused skills, including Layout Design and Custom Layout for analog and mixed-signal circuits.
Solid foundation in circuit-level skills such as Circuit Design, Analog, and Analog Circuits to understand design intent and constraints.
Hands-on experience with Physical Verification, including DRC, LVS, ERC, and related sign-off checks.
Experience with industry-standard EDA tools for analog layout and verification (e.g., Cadence Virtuoso, Mentor/Siemens, Synopsys tools).
Knowledge of semiconductor process technologies across multiple nodes (e.g., 65nm to advanced nodes) and their layout implications.
Proven ability to lead projects, review layouts, provide technical guidance, and mentor junior team members.
Strong analytical, problem-solving, and communication skills, with the ability to collaborate in cross-functional engineering teams.
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI,

Work arrangement
No