Analog Layout Engineer

Company Description SiMaxTech Pvt Ltd is a fast-growing semiconductor design services company that delivers end-to-end chip solutions to global customers. The organization combines deep expertise across the semiconductor value chain with a strong focus on high performance, quality, and accelerated time-to-market. Its engineering teams work across the full design spectrum, including analog circuit design, custom layout, physical design, AMS verification, and full-chip/SoC backend design, covering process technologies from 65nm up to 2nm and 18A. SiMaxTech promotes a culture of continuous learning and innovation, enabling professionals to work on next-generation products and cutting-edge nodes. With a customer-centric approach and a proven track record in high-quality design solutions, the company aims to be the preferred semiconductor design services partner for global clients.
Role Description The Analog Layout Engineer will be responsible for designing, implementing, and optimizing analog and mixed-signal layouts for integrated circuits, ensuring adherence to performance, reliability, and manufacturability requirements. Day-to-day tasks include translating circuit schematics into robust layouts, performing floorplanning, device matching, and routing, and running physical verification checks such as DRC, LVS, and EM/IR analysis. The role involves close collaboration with analog circuit designers, verification engineers, and physical design teams to resolve layout-related issues and support tape-out activities. The engineer will also contribute to layout methodology improvements, design reviews, and documentation to maintain best practices across projects. This is a full-time, on-site role based in Bengaluru South.
Qualifications
Candidates should possess strong skills in analog and mixed-signal IC layout, including transistor-level layout, matching techniques, floorplanning, and routing for blocks such as amplifiers, data converters, PLLs, and power management circuits.
Candidates should possess proficiency with industry-standard EDA tools for custom layout and physical verification (e.g., Cadence Virtuoso, Synopsys Custom Compiler, Mentor/Siemens Calibre for DRC/LVS, and EM/IR analysis tools).
Candidates should possess knowledge of semiconductor process technologies and design rules across various nodes (e.g., 65nm, 40nm, 28nm and below), with familiarity in advanced nodes (e.g., 7nm, 5nm, 3nm or beyond) considered an advantage.
Candidates should possess a solid understanding of analog circuit fundamentals, parasitics, layout-dependent effects, and techniques to optimize performance, area, and yield.
Candidates should possess effective collaboration and communication skills to work with cross-functional design, verification, and backend teams, along with strong problem-solving and attention-to-detail capabilities.
A bachelor’s or master’s degree in Electronics, Electrical Engineering, VLSI

Work arrangement
No