Live opening · Posted 14 days ago

Design Verification Engineer

Dabster · Bengaluru, Karnataka, India (On-site)
Linkedin No
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At a glance

The key details from the original listing.

Posted 14 days ago
CompanyDabster
LocationBengaluru, Karnataka, India (On-site)
Work modeNo
SkillsPython
SourceLinkedin
ListedPosted 14 days ago

About the role

Description supplied by the original job listing.

About Us:
At Dabster, we specialize in connecting top talent with leading global companies. We are currently seeking an experienced Design Verification Engineer to join our client’s team. Our mission is to be the foremost recruitment specialist in securing exceptional talent for a diverse range of global clients.
Who Will You Work With:
Our client is a global technology leader working on advanced semiconductor and system-on-chip (SoC) designs. You will join a high-performing engineering team focused on delivering best-in-class verification solutions for complex SoCs and IPs within the ARM ecosystem.
About the Role:
As a Design Verification Engineer/Lead, you will be responsible for end-to-end SoC verification, working on ARM-based systems and high-speed interconnects. You will leverage your expertise in UVM, SystemVerilog, and scripting to design and execute verification plans, ensuring first-time-right silicon. The initial contract is for 6 months, with strong potential for multiple extensions.
Key Responsibilities:
Perform SoC-level verification within the ARM ecosystem.
Develop and execute verification strategies for PCIe and related IPs.
Work with PCIe VIPs and carry out GLS (Gate-Level Simulation) tasks.
Write and maintain verification testbenches in SystemVerilog/UVM.
Contribute to automation through Python scripting.
Collaborate with cross-functional teams while following modern development practices using GIT.
Share knowledge and work effectively within a distributed engineering team.
Preferred Skills:
Strong SoC verification experience in ARM-based designs.
Hands-on experience with PCIe and PCIe-VIP usage.
Proficiency in C, SystemVerilog, and UVM methodologies.
Familiarity with Gate-Level Simulations (GLS).
Working knowledge of GIT for version control.
Solid scripting experience, especially with Python.
Excellent communication skills and a willingness to learn.
What We Offer:
Impactful Work: Contribute to complex, cutting-edge SoC design and verification for a global technology leader.
Location: Pan India
Contract Type: 6-month contract with possibilities of multiple extensions.
Interview Process:
Expect one or two rounds of technical discussions, followed by a business-focused round.

Work arrangement
No

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