RTL Engineer

Role: RTL Design Engineer
Location: Bangalore / Hyderabad
Experience: 3–8 Years
Shift: Regular
Education: B.E/B.Tech/M.Tech in Electronics, VLSI, or related field
Role Overview
We are seeking skilled RTL Design Engineers to join our team in Bangalore/Hyderabad. In this role, you will contribute to RTL coding, design integration, and validation for advanced semiconductor projects. You will collaborate with cross‑functional teams and gain exposure to industry‑standard tools and methodologies.
Key Responsibilities
Develop and maintain RTL code in Verilog/SystemVerilog
Collaborate with design and verification teams to ensure functional correctness
Support integration, synthesis, and timing closure activities
Debug and resolve RTL design issues efficiently
Required Skills
Strong expertise in RTL Design
Proficiency in Verilog/SystemVerilog
Solid understanding of digital logic design, FSMs, and timing concepts
Exposure to synthesis, STA, and RTL methodologies
Familiarity with EDA tools and scripting (TCL, Perl, Python preferred)
Good to Have
Knowledge of low‑power design techniques, clocking, and resets
Prior exposure to industry‑leading design flows
Soft Skills
Strong verbal and written communication skills
Ability to manage multiple deliverables in a fast‑paced environment

Work arrangement
No