Live opening · Posted 4 days ago
Senior Verification Engineer, DDR PHY (IRT60ST RM 4494)
Source-Right · Bengaluru, Karnataka, India (On-site)
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At a glance
The key details from the original listing.
CompanySource-Right
LocationBengaluru, Karnataka, India (On-site)
Work modeNo
Source
Linkedin
ListedPosted 4 days ago
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About the role
Description supplied by the original job listing.
Position: Senior Verification Engineer, DDR PHY (IRT60ST RM 4494)
Verification ownership from testplan to vector delivery, regression debug, and quality sign-off for DDR PHY.
Must-have
DDR PHY architecture, DFI protocol, JEDEC standards (latest gens)
LPDDR5/LPDDR4 hands-on experience
Verilog/SystemVerilog, UVM/OVM
Strong debug and root-cause skills, including SS/SoC/post-silicon issues
Good To Have
Perl scripting
Post-silicon bring-up, HW-SW debug
AHB/AXI protocol knowledge
Work arrangement
No
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