Senior Physical Design Manager

Company Description SignOff Semiconductors Pvt. Ltd. is a VLSI design services company headquartered in Bangalore, India, providing high-quality semiconductor design solutions to global fabless companies, IDMs, ASIC developers, and SoC innovators. Founded in 2015 by industry professionals from Intel and AMD, the company is built on strong values of quality, commitment, and predictable first-pass silicon success. SignOff delivers end-to-end ASIC and SoC design services from specification to GDSII through flexible engagement models such as Offshore Development Centers, dedicated engineering teams, turnkey projects, and staff augmentation. Its core expertise includes RTL design, functional verification, DFT, physical design, STA, low-power design, analog/mixed-signal design, and IP integration across advanced nodes from 2nm to 28nm and beyond. With a focus on engineering excellence and customer-centric delivery, SignOff supports next-generation AI, networking, automotive, HPC, data center, wireless, and custom ASIC programs for leading semiconductor companies worldwide.
Role Description The Senior Physical Design Manager will lead and oversee complex RTL-to-GDSII implementation flows, managing physical design teams responsible for block- and full-chip layout, floorplanning, place-and-route, timing closure, and signoff. This full-time, on-site role based in Bengaluru South involves planning project execution, defining methodologies, setting quality standards, and coordinating with RTL, verification, DFT, and analog teams to ensure seamless integration and tape-out readiness. The person in this role will review design constraints, optimize performance, power, and area (PPA), drive timing and congestion closure, and manage risks and escalations across multiple projects and technology nodes. They will also mentor engineers, support technical training, contribute to flow and script development, and collaborate with customers to clarify requirements, present status updates, and support signoff reviews. The role requires strong technical leadership, hands-on problem-solving, and the ability to manage schedules and deliverables in a fast-paced semiconductor design environment.
Qualifications
Expert-level skills in Physical Design, including floorplanning, place-and-route, clock tree synthesis, and layout optimization.
Strong experience in Timing analysis, Static Timing Analysis (STA), timing closure, and signal integrity across advanced technology nodes.
Hands-on expertise in Power Analysis, power optimization, and low-power design techniques for complex ASIC and SoC designs.
Proficiency in Physical Verification, including LVS, DRC, and other signoff checks using industry-standard EDA tools.
Solid understanding of RTL Design fundamentals, constraints definition (SDC), and interaction with RTL and DFT teams.
Experience leading physical design teams, managing project schedules, and delivering production-quality designs from spec-to

Work arrangement
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