Design for Testability Engineer

Job Description
DFT architecture, implementation ownership, Own -milestones, dependencies and delivery, all stakeholder coordination
Key Responsibilities
1) Define DFT architecture and implementation methodology
2) Own scan architecture, insertion and closure
3) Define ATPG strategy, fault models and coverage targets
4) Develop/review DFT RTL and drive integration
5) Define verification strategy and drive closure
6) Own pattern simulation and debug
Skill Requirements
1) Extensive SoC-level debug and root-cause analysis
2) Strong SoC tapeout experience and DFT sign-off ownership
3) Strong hands-on Tessent/ATPG and DFT implementation tools
4) Develop and maintain DFT automation/scripts"

Work arrangement
Yes