GLS Verification Engineer

Company Description Core ASIC Inc is a customer-focused VLSI design and verification services company with operations in Bengaluru, India and Austin, Texas. The company delivers complete spec-to-silicon turnkey solutions, including firmware co-development, for custom semiconductor and IoT applications. Its silicon-proven platform solutions support IP design and verification, VIP development, SoC verification, and emulation services. Core ASIC emphasizes on-time delivery, strong client collaboration, and alignment with customer vision to improve time-to-market and return on investment. A dedicated team of engineering, technology, and domain experts works as a growth partner to clients across the product development lifecycle.
Experience:5-10 years
Key Skills
Gate Level Simulation, SDF Annotation, Timing Verification, Low Power Verification, Debugging, Verdi, VCS, Xcelium
Detailed Job Description
Execute gate-level simulations with and without SDF, perform timing validation, low-power checks, reset verification and debug GLS failures. Analyze setup/hold violations and work closely with STA, RTL and Physical Design teams to achieve sign-off.
Role Description The GLS Verification Engineer is responsible for gate-level simulation and verification of complex digital designs, ensuring functional correctness, timing closure, and manufacturability. Day-to-day tasks include creating and executing GLS test plans, developing verification environments and testbenches, running regressions, analyzing waveforms, and debugging failures across RTL and gate-level netlists. The role involves close collaboration with RTL design, physical design, DFT, and validation teams to resolve issues, support sign-off, and improve verification methodologies. The engineer will also contribute to documentation, process improvements, and best practices for GLS and functional verification. This is a full-time, on-site role based in Bengaluru and Hyderabad
Qualifications
Strong experience in RTL Design and Functional Verification for complex digital ASIC/SoC projects.
Proficiency in Debugging simulation failures, timing issues, and gate-level mismatches.
Knowledge of Validation processes and methodologies for pre-silicon and post-silicon environments.
Understanding of Good Manufacturing Practice (GMP) or equivalent quality and reliability standards in semiconductor development.
Hands-on experience with GLS flows, STA concepts, and EDA tools (e.g., simulation, lint, formal verification).
Familiarity with Verilog/SystemVerilog, scripting languages (such as Python, Perl, or TCL), and regression automation.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
Strong analytical and problem-solving skills, attention to detail, and ability to collaborate in cross-functional engineering teams.
Experience in VLSI design services or semiconductor product companies is an advantage.

Work arrangement
No