Principal Engineer, AMS Circuit Design – High-Speed SerDes

an early-stage engineering team
Staff / Principal Engineer, Analog/Mixed-Signal Design – High-Speed
SerDes
Full-time | Bengaluru or Hyderabad, India (Hybrid) | Analog/Mixed-Signal Design
About the Team
Stealth mode start-up
Bangalore/Hyderabad
Staff / Principal Engineer, Analog/Mixed-Signal Design – High-Speed
SerDes
Full-time | Bengaluru or Hyderabad, India (Hybrid) | Analog/Mixed-Signal Design
About the Team
We are an early-stage engineering team building high-bandwidth, low-power interconnect for next-
generation compute and datacenter systems, spanning die-to-die links and 224G-class electrical SerDes.
We are looking for an experienced analog/mixed-signal designer to take ownership of key circuits in our
PHYs and help carry them from architecture through silicon. This is a small, hands-on team: you will own
your blocks end to end, from specification and design through layout, tapeout, and lab bring-up, and
have a direct say in architecture and product decisions.
What You'll Be Doing
• Own the design of one or more high-speed analog/mixed-signal blocks for our SerDes PHYs,
from specification and architecture through schematic design, simulation, and post-layout sign-
off.
• Contribute across the PHY, including transmitter (serializer, driver, DAC-based TX, FFE), receiver
(CTLE, DFE, samplers, ADC-based front end), clocking (PLL/DLL, phase interpolator, duty-cycle
correction, CDR or forwarded clock), and supporting circuits (termination, deskew, bias,
references).
• Derive block-level specifications and budgets for jitter, noise, linearity, power, and area from
link-level requirements, working closely with the architecture team.
• Verify designs across PVT corners, Monte Carlo, and extracted parasitics, including EM/IR and
reliability checks.
• Guide layout engineers on floorplanning, matching, and critical routing.
• Partner with SI/package, DSP, digital, and verification teams on calibration, link training, and
adaptation, and provide behavioral models for system-level simulation.
• Support silicon bring-up, lab characterization, and debug.
• Lead design reviews and mentor junior engineers.
What We Need to See
• MS or PhD in Electrical Engineering (or equivalent) and 8+ years in analog/mixed-signal IC
design.
• High-speed SerDes or I/O circuits taken to production silicon in advanced FinFET nodes.
• Strong fundamentals in noise, jitter, equalization, and clocking.
• Hands-on with Synopsys or Cadence custom IC design and simulation flows, including post-
layout simulation.
• Clear communicator across architecture, digital, and package teams.
• Comfortable owning your blocks end to end in a small team, lab work included.Ways to Stand Out from the Crowd
• Experience with 112G/224G PAM4 SerDes, including ADC/DSP-based receivers or DAC-based
transmitters.
• Experience with die-to-die interconnect standards such as UCIe.
• Familiarity with advanced packaging and package/interposer signal integrity.
• Experience with calibration and adaptation loops and mixed-signal co-design.
• Python, SKILL, or similar scripting to automate simulation, regression, and data analysis,
including AI/LLM-based agents applied to design workflows.
• Hands-on silicon bring-up and lab characterization experience.
Contact:Uday
Mulya Technologies
"Minining the knowledge community"
muday_bhaskar@yahoo.com

Work arrangement
Hybrid