Senior Layout Design Engineer

Title: Senior Layout Design Engineer
Organization: Top 100 Semiconductor Organization
Location: Greater Bengaluru Area
Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.
Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, We are changing the timing industry. For more information.
Job Summary
The Senior Layout Design Engineer will lead top-chip, block-level and perform custom Analog Layout Design for CMOS and BiCMOS circuits. This role includes reviewing and coordinating work performed by offshore layout designers, training junior layout engineers and offshore contractors, contributing to the development of standard layout methodologies across sites, and helping establish processes and procedures that ensure high-quality layout design
Responsibilities
Collaborate remotely with local and global design and layout teams across multiple design centers and time zones
Lead and perform custom analog layout design at the chip and functional block, block, sub-block, leaf cell, and standard cell levels for CMOS and BiCMOS circuits
Execute schematic-driven layout design while adhering to design constraints
Create area-efficient functional block layouts that meet circuit design requirements
Develop top-chip and block-level floor plans, power distribution networks, shielding structures, and device-matching layouts
Verify layouts and ensure successful DRC, LVS, and ERC signoff
Perform chip-level routing and other layout-related activities
Own chip-chip integration, verification, and tape-out activities
Provide support for additional projects as required by management
Train and mentor junior layout engineers and offshore layout contractors
Contribute to the development of common best practices and workflows across all sites
Help establish and improve processes and procedures to achieve high layout quality
Qualifications & Requirements
BA/BS degree in Layout Design or a related field, or equivalent experience
8+ years of experience in layout design for analog and full-custom digital blocks
Experience with TSMC 180nm, 65nm, 22nm process technologies
Proficiency with layout editing tools in the Cadence Virtuoso design environment
Solid working knowledge of DRC, LVS, and ERC debugging using Cadence PVS or Mentor Calibre
Understanding of layout concepts, including parasitics, matching, crosstalk, layout-dependent effects, latch-up, IR drop, electromigration (EM), and deep N-well and NTN isolation
Strong ability to solve device matching, electromigration, signal integrity, and power distribution challenges while meeting area constraints
Experience with chip-level floorplanning and analog block integration
Experience with chip-level integration, verification, and tape-out
Ability to use productivity-enhancing tools and design scripts to automate and improve workflow efficiency
Must be able to lift, push, and pull up to 5 lbs
Desired Characteristics & Attributes
Strong attention to detail; organized, accurate, and able to develop efficient layout techniques
Proven track record of delivering work on time
Self-motivated team player with strong communication skills
Ability to work effectively in a fast-paced, collaborative team environment
Contact : SUMIT S. B.
sumit@mulyatech.com
www.mulyatech.com
Mulya Technologies
"Mining the Knowledge Community"

Work arrangement
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