Live opening · Posted 6 hours ago
At a glance
The key details from the original listing.
About the role
Description supplied by the original job listing.
Job Description: Mandatory skills- P&R, timing, power/voltage analysis, and leadership.Physical Design experience with 3+ years of experience in ASIC/SoC Physical Design. Candidate should have strong hands-on expertise in Cadence Innovus, Synopsys Fusion Compiler, and Primetime, with experience in timing closure, PPA optimization, physical implementation, and signoff. Experience with Voltage/IR-drop and power integrity analysis tools is required.
Responsibilities
Physical Design experience with 3+ years of experience in ASIC/SoC Physical Design.
Candidate should have strong hands-on expertise in Cadence Innovus, Synopsys Fusion Compiler, and Primetime, with experience in timing closure, PPA optimization, physical implementation, and signoff.
Experience with Voltage/IR-drop and power integrity analysis tools is required.
Required Skills
Mandatory skills- P&R, timing, power/voltage analysis, and leadership.
Work arrangement
Hybrid
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