ASIC Digital Verification Engineer: Ethernet / UFS / UniPro / USB (IP Verification)

The Synopsys Digital IP R&D team is hiring experienced ASIC/IP Verification Engineers (2 to 5 years) to work on advanced connectivity protocols, including Ethernet / UFS / UniPro / USB / MPhy, across commercial, enterprise, and automotive applications.
Job Role
What You'll Be Doing:
Be part of the Synopsys IP Verification R&D team at our Bangalore R&D Center, working closely with the RTL design team within a global team of expert Verification Engineers
Contribute to end-to-end verification of subsystems with high-speed interconnect IPs, including one or more of controllers and Phy IP related to protocols such as Ethernet / UFS / UniPro / USB / MPhy, from test planning to coverage closure and sign-off
Develop and use state-of-the-art verification environments for the Synopsys IP family of synthesizable cores, and perform verification tasks on these IP cores
Understand compliance testing standards and build simulation-based compliance test suites
Develop SystemVerilog/Verilog testbenches and test cases; run regressions, analyze coverage, and debug failures using methodologies such as UVM and formal verification
Cover test planning, unit-level and system-level test environment coding, test case coding and debugging, Controller-PHY IP interoperability testing, and regression management
Beyond traditional verification, you’ll have the opportunity to work with frontier AI models and build agentic workflows for verification, from automated testbench creation and test planning to coverage analysis and closure.
Contribute to IP development used in high-performance computing, communications, servers, consumer devices, and automotive applications that power the technologies of tomorrow
Collaborate across design, architecture, and validation teams and drive issues to resolution
Requirements:
What You'll Need:
Engineering degree / Post graduation (B.Tech / M.Tech) with 2–5 years of verification experience
Hands on experience with coding in Verilog, System Verilog and methodology such as UVM
Controller–PHY integration / interoperability simulation experience is a strong plus
Prior experience in usage of industry standard VIP is a definite advantage
Experience with SVA assertions, functional coverage, and coverage-driven verification
Strong debug skills using Verdi (waveform + transaction/protocol-level analysis, RCA)
Proficiency in one or more structured programming languages such as C, C++, Python.
Experience building AI agents, agentic workflows, and AI-driven engineering automation will be a distinct advantage
Strong analytical thinking, problem-solving ability, debugging skills, and attention to detail
Ability to collaborate across design/architecture/validation teams and drive issues to resolution
Effective written and oral communication is a must; Good interpersonal skills for working in a geographically distributed team
High levels of motivation, curiosity, and a self-driven approach to learning
If you are interested in verifying production-quality IP that ships into real silicon and directly impacts first pass-silicon success, please connect or reach out.
Synopsys is committed to creating an inclusive workplace and is an equal opportunity employer. We welcome all qualified applicants to apply, regardless of age, color, gender identity or expression, marital status, disability, race and ethnicity, religion, sexual orientation, or any other characteristic protected by local laws. If you need assistance or a reasonable accommodation during the application process, please reach out to us.
Working Model: Onsite; Full-Time, In-office 4-5 days per week

Skills
Python, C++

Experience
2-5 yrs