RTL Engineer

Responsibilities:
Translate the architecture specification into synthesizable SystemVerilog.
Own the RTL coding standards, linting rules, and design methodology.
Lead a team of 5-7 RTL engineers through the full design cycle.
Own the synthesis flow (Design Compiler or Genus) and drive timing closure.
Define and maintain SDC timing constraints.
Review all RTL code submissions for correctness, synthesizability, and style.
Coordinate with the outsource partner on GDSII handover (netlist, constraints, and floorplan guidance).
Work closely with the verification team to resolve bugs and achieve coverage closure.

Experience
10-14 yrs