Sr. Verification Engineer (RTL)

As a Senior RTL Verification Engineer, you will drive verification strategy and execution for complex RTL designs, working closely with architects, RTL designers, firmware, compiler, and software teams. You will own the process from specification and verification planning through coverage closure and silicon readiness, while helping build scalable verification methodologies for Anthriq's next-generation silicon platform.
Responsibilities:
Own verification strategy, planning, execution, and sign-off for complex IPs and SoC subsystems.
Develop scalable and reusable SystemVerilog/UVM verification environments.
Define test plans, verification metrics, coverage goals, and closure strategies.
Develop constrained-random, directed, assertion-based, and corner-case tests.
Build functional coverage models and drive coverage closure.
Develop and maintain SystemVerilog Assertions (SVA) and contribute to formal verification.
Debug complex RTL, simulation, and system-level failures and drive issues to closure.
Verify high-performance datapaths, pipelines, vector processing units, memory systems, interconnects, and control logic.
Work closely with architecture and RTL teams to identify design risks and corner cases early.
Drive verification at block, subsystem, and SoC levels.
Improve verification infrastructure, regression frameworks, automation, and methodologies.
Participate in design reviews, verification reviews, and silicon readiness/sign-off activities.
Mentor junior and mid-level verification engineers and contribute to building a strong verification culture.
Requirements:
8+ years of experience in ASIC/SoC/RTL verification.
Strong hands-on expertise in SystemVerilog and UVM.
Strong understanding of digital design, computer architecture, and RTL fundamentals.
Proven experience owning verification of complex IPs or SoC subsystems.
Strong expertise in constrained-random verification, functional coverage, and coverage closure.
Strong experience with SVA and assertion-based verification.
Excellent RTL and simulation debugging skills.
Experience with industry-standard tools such as VCS, Verdi, Questa, or equivalent.
Strong programming/scripting skills in Python, Perl, C/C++, or Shell.

Experience
8-12 yrs