Analog Layout Engineers - Seniors

Company Description SiMaxTech Pvt Ltd is a fast-growing semiconductor design services company that delivers end-to-end chip solutions for global customers. The organization offers strong capabilities across the semiconductor design spectrum, including analog circuit design, custom layout, physical design, and embedded design. With experience spanning mature to cutting-edge process technologies from 65nm to advanced nodes like 2nm and 18A, the team focuses on high performance, quality, and faster time-to-market. SiMaxTech is driven by a culture of continuous learning and innovation, with a mission to provide best-in-class engineering services throughout the chip development lifecycle. The company aims to be the preferred semiconductor design partner, emphasizing a customer-centric approach, reliability, and scalable solutions.
Role Description This is a full-time, on-site role for Senior Analog Layout Engineers based in Bengaluru South. The role involves designing and implementing high-quality analog and mixed-signal layout for complex circuits, ensuring adherence to design rules, performance targets, and manufacturing constraints. Responsibilities include working closely with circuit design engineers to translate schematics into optimized layouts, performing floorplanning, device matching, parasitic optimization, and latch-up/EM considerations. The role also requires running and reviewing physical verification checks (DRC, LVS, ERC) and collaborating with cross-functional teams to resolve layout and sign-off issues. Senior engineers are expected to mentor junior team members, contribute to layout methodology improvements, and support project planning and delivery across multiple technology nodes.
We're Hiring,
Analog Layout Engineers
Experience: 4+Years
Location: Bangalore and Hyderabad
Notice Period: Immediate Joiners
Qualifications
Candidates should possess strong skills in Layout Design and Custom Layout for analog and mixed-signal blocks.
Candidates should possess solid Circuit Design understanding, including Analog and Analog Circuits fundamentals.
Candidates should possess expertise in Physical Verification, including DRC, LVS, ERC, and reliability checks.
Experience with industry-standard EDA tools (e.g., Cadence Virtuoso, Mentor/Siemens, Synopsys) for layout and verification.
Hands-on experience across multiple technology nodes (preferably 65nm and below; exposure to advanced nodes is a plus).
Bachelor’s or Master’s degree in Electrical/Electronics Engineering or a related discipline.
Ability to work collaboratively in a multidisciplinary engineering environment and mentor less experienced team members.
Strong problem-solving skills, attention to detail, and commitment to high-quality, first-time-right design execution.

Work arrangement
No