Analog Layout Engineer

Company Description SiMaxTech Pvt Ltd is a fast-growing semiconductor design services company that delivers end-to-end chip solutions for global customers. The company offers deep expertise across the semiconductor value chain, supporting next-generation products with high performance, quality, and accelerated time-to-market. Its engineering team covers a wide spectrum of design capabilities, including analog circuit design, custom layout, physical design, and embedded design. SiMaxTech works across mature and advanced process technologies, from 65nm and above to cutting-edge nodes such as 7nm, 5nm, 3nm, and emerging nodes like 2nm and 18A. Guided by a vision to be a preferred global partner, the company emphasizes continuous learning, innovation, and a customer-centric approach focused on reliability and scalability.
Role Description The Analog Layout Engineer role is a full-time, on-site position based in Bengaluru South. The person in this role will be responsible for creating and optimizing analog and mixed-signal layout designs, ensuring that circuit performance, matching, and area constraints are met. Day-to-day tasks include working closely with circuit designers to interpret schematics, perform floorplanning, device placement, routing, and ensuring compliance with design rules. The role involves running and reviewing physical verification checks such as DRC, LVS, and ERC, addressing layout-related issues, and iterating designs for manufacturability and yield. The Analog Layout Engineer will collaborate with cross-functional teams, maintain documentation, and contribute to design reviews and continuous improvement of layout methodologies.
Qualifications
Candidates should possess strong skills in Layout Design and Custom Layout for analog and mixed-signal circuits.
Candidates should possess solid expertise in Circuit Design, including Analog and Analog Circuits.
Candidates should possess experience in Physical Verification, including DRC, LVS, ERC, and related sign-off flows.
Familiarity with industry-standard EDA tools (e.g., Cadence Virtuoso, Mentor/Siemens, Synopsys) for layout and verification.
Understanding of semiconductor process technologies across multiple nodes (e.g., 65nm and below) and their layout constraints.
Ability to interpret schematics, design specifications, and apply layout best practices for matching, noise, and reliability.
Strong analytical skills, attention to detail, and ability to work collaboratively in a fast-paced engineering environment.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field, or equivalent practical experience.

Work arrangement
No