VLSI & Semiconductor Designing-Faculty

POSITION SUMMARY Position title Faculty / Trainer — VLSI & Semiconductor Design ROLE PURPOSE To deliver and assess classroom and laboratory training in VLSI and semiconductor design, maintain the EDA lab environment, and prepare learners for direct entry into industry design, verification and implementation roles.
KEY RESPONSIBILITIES
• Deliver theory and hands-on laboratory sessions on live enterprise EDA tools as per the approved scheme of work.
• Prepare session plans, lab exercises, reference designs, scripts and model solutions ahead of delivery. • Guide learners through debugging — simulation failures, synthesis and timing violations, layout and physical verification errors, hardware faults.
• Design and mark assignments, projects, viva questions and entry-level screening tests; provide documented feedback.
• Maintain assessment records, attendance and learner progress data; support internal verification and quality audits.
• Supervise capstone and industry projects through to a working, demonstrable outcome.
• Install and maintain EDA tools, licence servers, workstations, development boards and the Linux lab environment.
• Update curriculum content in line with current industry tools, process nodes and methodologies.
• Support placement activity: mock technical interviews, portfolio review and employer interaction. TECHNICAL REQUIREMENTS
Demonstrable hands-on capability in at least one of the following areas, sufficient to build a working flow independently:
• Digital & FPGA: digital logic, Verilog/VHDL RTL, FSM design, testbenches, simulation, synthesis, timing constraints, board-level implementation and debug.
• Verification: SystemVerilog, assertions, constrained-random and coverage-driven methodology, UVM testbench architecture, formal verification.
• Physical design & sign-off: floorplanning, power planning, placement, clock tree synthesis, routing, static timing analysis, ECO closure, DRC/LVS, IR drop and electromigration checks.
• DFT: fault modelling, scan insertion, ATPG, MBIST, JTAG, fault coverage analysis.
• Analog & mixed signal: CMOS device physics, amplifier design, data converters, PLL, custom layout, parasitic extraction, post-layout simulation. • Tools: working proficiency in industry-standard EDA suites (Synopsys, Cadence, Siemens, Xilinx/AMD or equivalent) relevant to the chosen area.
• Scripting: Tcl, plus Python or Perl, for flow automation, regressions and report generation. Linux command-line proficiency.
ESSENTIAL REQUIREMENTS
• Verifiable individual contribution to a completed tape-out, verification sign-off, timing closure or shipped hardware product.
• Ability to explain complex technical concepts clearly in English to a mixed-ability graduate cohort.
• Willingness to teach live on tools, including unscripted debugging in front of a class.
• Availability on-site for the full duration of assigned batches, including assessment periods.

Work arrangement
No