Physical Design Engineer

Company Description Corp Match Private Limited is a placement-focused training and hiring ecosystem dedicated to transforming students into industry-ready professionals. The company partners with colleges and organizations across India to bridge the gap between academic learning and corporate expectations through structured, outcome-driven programs. Its services include IT and non-IT skill development, financial domain specialization, corporate readiness and interview preparation, campus hiring partnerships, and industry-aligned certification programs. Corp Match works closely with educational institutions to enhance placement success, with companies to provide trained and reliable talent, and with students to accelerate career growth. The mission is to reduce the skill gap, improve employability, and create meaningful career opportunities nationwide.
Role Description The Physical Design Engineer role at Corp Match Private Limited is a full-time, on-site position based in Bengaluru South. The engineer will be responsible for translating logical design into physical layouts, performing floorplanning, placement, clock tree synthesis, routing, and optimization for timing, power, and area. Daily tasks include running and analyzing static timing, signal integrity, power, and physical verification checks, identifying design bottlenecks, and collaborating with front-end, architecture, and verification teams to resolve issues. The role also involves preparing documentation, maintaining design flows, supporting tape-out activities, and contributing to continuous improvement of methodologies and tools used in physical design.
Qualifications
Candidates should possess strong skills in physical design implementation, including floorplanning, placement, clock tree synthesis, routing, and timing closure.
Candidates should possess expertise in analysis tools and methodologies such as static timing analysis, power analysis, signal integrity checks, and physical verification (DRC/LVS).
Candidates should possess familiarity with industry-standard EDA tools (e.g., Cadence, Synopsys, or Mentor graphics tools) and scripting skills in languages such as Tcl, Perl, or Python.
Candidates should possess solid understanding of digital design concepts, CMOS fundamentals, VLSI design principles, and interfaces with front-end RTL and verification flows.
Candidates should possess strong problem-solving abilities, attention to detail, and effective communication skills for collaboration in cross-functional engineering teams.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or a related discipline is preferred, along with prior experience or projects in ASIC/SoC physical design.
Experience working in high-performance, low-power designs, familiarity with advanced technology nodes, and exposure to tape-out processes will be considered an advantage.

Work arrangement
No