DFT Engineer

Company Description Corp Match Private Limited (Corpmatch) is a placement-focused training and hiring ecosystem dedicated to transforming students into industry-ready professionals. The company partners with colleges and organizations to bridge the gap between academic learning and corporate expectations through structured, outcome-driven programs. Corpmatch offers IT and non-IT skill development, financial domain specialization, corporate readiness training, interview preparation, and industry-aligned certifications. By closely collaborating with educational institutions, employers, and learners, Corpmatch builds sustainable talent pipelines across India. Its mission is to reduce the skill gap, improve employability, and create meaningful career opportunities while aligning education with real industry requirements.
Role Description The DFT Engineer will work on design-for-testability implementation and verification for complex integrated circuits in an on-site, full-time role located in Bengaluru South. Responsibilities include developing and integrating DFT architectures such as scan insertion, boundary scan, and built-in self-test (BIST), and collaborating with design and verification teams to ensure test coverage and quality. The role involves generating and validating test patterns, analyzing fault coverage, and optimizing test strategies for manufacturability and yield improvement. The DFT Engineer will also support debug activities, work with fabrication and test teams, and contribute to documentation and process improvements aligned with industry standards.
Qualifications
Strong knowledge of DFT concepts and methodologies, including scan, boundary scan, BIST, and ATPG.
Proficiency in hardware description languages such as Verilog or VHDL, and familiarity with RTL design flows.
Hands-on experience with EDA tools for DFT implementation, test insertion, and pattern generation (e.g., Synopsys, Cadence, or equivalent).
Understanding of digital logic design, SoC/ASIC design flows, and semiconductor manufacturing test processes.
Ability to analyze fault coverage reports, debug test failures, and optimize test plans for quality and efficiency.
Strong problem-solving skills, attention to detail, and ability to collaborate effectively in cross-functional engineering teams.
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or a related technical discipline.
Exposure to scripting languages (such as Python, Perl, or TCL) for automation and flow optimization is an advantage.
Prior internship or professional experience in DFT, ASIC design, or related semiconductor domains is preferred.

Work arrangement
No