Physical Design Engineer

Company Description Corp Match Private Limited is a placement-focused training and hiring ecosystem committed to transforming students into industry-ready professionals. The company partners with colleges and corporations across India to bridge the gap between academic learning and real-world corporate expectations. Through structured IT and non-IT programs, financial domain training, interview preparation, and industry-aligned certifications, Corp Match creates measurable placement outcomes and sustainable talent pipelines. By closely collaborating with institutions, companies, and students, the organization focuses on reducing the skill gap, improving employability, and enabling meaningful career opportunities. Corp Match’s mission is to ensure education leads to employment and to help build the future workforce through practical, result-driven execution.
Role Description The Physical Design Engineer role at Corp Match Private Limited is a full-time, on-site position based in Bengaluru. The engineer will be responsible for RTL-to-GDSII implementation, including floorplanning, placement, clock tree synthesis, routing, and timing closure for complex SoC or ASIC designs. Daily tasks include running physical verification (DRC/LVS), power analysis, signal integrity checks, and ensuring designs meet performance, area, and power targets. The role involves collaborating with front-end design, verification, and DFT teams to resolve design issues, optimize constraints, and maintain design quality throughout the implementation flow. The engineer will also support tape-out activities, contribute to methodology and flow improvements, and document design processes and best practices.
Qualifications
Candidates should possess strong skills in physical implementation flows such as floorplanning, placement, clock tree synthesis, and routing.
Candidates should possess skills in static timing analysis, timing closure, and optimization for performance, power, and area.
Candidates should possess skills in physical verification, including DRC, LVS, and electromigration/IR drop analysis.
Candidates should possess familiarity with industry-standard EDA tools (e.g., Cadence, Synopsys, or Mentor) used in physical design.
Candidates should possess a solid understanding of digital design fundamentals, CMOS concepts, and RTL-to-GDSII flows.
Candidates should possess effective communication, problem-solving, and collaboration skills to work with cross-functional engineering teams.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or a related field is preferred.
Relevant experience in ASIC/SoC physical design, tape-out, or internships in semiconductor/VLSI companies will be beneficial.

Work arrangement
No