Design Verification - Technical Leader

OUR STORY
At STMicroelectronics, we believe in the power of technology to drive innovation and make a positive impact on people, businesses, and society. As a global semiconductor company, our advanced technologies and chips form the hidden foundation of the world we live in today.
When you join ST, you will be part of a global business with more than 115 nationalities, present in 40 countries, and comprising over 50,000 diverse and dedicated creators and makers of technology around the world.
Developing technologies takes more than talent: it takes amazing people who understand collaboration and respect. People with passion and the desire to disrupt the status quo, drive innovation, and unlock their own potential.
Embark on a journey with us, where you can innovate for a future that we want to make smarter and greener, in a responsible and sustainable way. Our technology starts with you.
About The Role
We are seeking an experienced Digital Verification Engineer to take on a Technical Leader role within our Imaging verification team. The candidate will drive verification strategy and closure for complex digital IPs in imaging and automotive subsystems, mentor junior engineers, and act as the technical point of contact for verification across cross-functional teams.
Key Responsibilities
Own end-to-end verification strategy, planning, and closure for one or more complex IPs/subsystems.
Architect and review UVM-based verification environments, ensuring reusability and scalability across projects.
Drive functional and code coverage closure; define coverage models and identify verification gaps early in the cycle.
Lead protocol-level verification efforts (e.g., I3C, MIPI, AMBA), including VIP evaluation, integration, and debug.
Apply the use of formal verification techniques (e.g., JasperGold) to complement simulation-based verification, particularly for FSM and control-logic-heavy blocks.
Review test plans, testbenches, and verification collateral authored by team members; provide technical guidance on methodology and debug approaches.
Interface with design, architecture, DFT, and software teams to clarify specification ambiguities and drive design-for-verification practices.
Identify and resolve spec ambiguities/errata; work with IP/protocol working groups where applicable.
Mentor and technically guide junior verification engineers; support their ramp-up on tools, methodology, and protocols.
Drive process improvements: regression infrastructure, debug efficiency, coverage methodology, and verification reuse.
Communicate verification status, risks, and closure plans to management and stakeholders.
Support root-cause analysis of silicon/post-silicon issues traced back to verification gaps, where relevant.
Required Skills
Bachelor's/Master's degree in Electronics, Electrical, or Computer Engineering (VLSI specialization preferred).
5-7 years of experience in digital design/IP verification, with demonstrated ownership of verification closure for at least one complex IP or subsystem.
Strong expertise in System Verilog and UVM methodology — testbench architecture, sequences, scoreboards, and reference models.
Proven experience with functional coverage, code coverage, and assertion-based verification (SVA); ability to define coverage models from specification.
Hands-on experience with industry-standard simulation tools (VCS, Xcelium, or Questa) and debug tools.
Experience with formal verification tools and methodology (e.g., JasperGold) for FSM, connectivity, or control-logic verification.
Solid understanding of one or more protocols such as I3C, I2C, SPI, AMBA,MIPI-CSI, or similar interconnect/interface standards, including VIP-based verification.
Strong scripting skills (Python, Perl, or TCL) for automation, flow development, and regression management.
Ability to read and interpret design specifications, RTL, and identify verification risk areas independently.
Preferred / Good To Have
Experience mentoring or technically leading a small team of verification engineers.
Exposure to mutation testing or other coverage-quality assessment techniques.
Familiarity with low-power verification (UPF/CPF) and Gate Level simulations.
Experience working with EDA vendors (e.g., Cadence, Synopsys) for tool/methodology support and issue resolution.
Prior contribution to internal verification methodology documents, guidelines, or reusable verification IP (VIP) development.
Experience working in a globally distributed team environment.
Soft Skills
Strong technical leadership and mentoring ability.
Excellent problem-solving and debugging skills, with the ability to work through ambiguous or under-specified requirements.
Strong written and verbal communication skills — able to present technical status and risk clearly to management.
Ownership mindset with the ability to work independently and drive closure under deadlines.
Collaborative approach to working with design, architecture, and cross-functional teams.
Exposure to AI/ML assisted verification techniques to improve verification productivity and efficiency.
What We Offer
A technical leadership track with visibility into IP-level and subsystem-level verification strategy.
Opportunity to shape verification methodology, including formal and protocol verification practices.
Mentorship and people-development opportunities within a growing team.
Exposure to advanced verification domains including formal verification and next-generation Security IP and systems.
Collaborative, cross-functional work environment with global teams.
ST is proud to be one of the 17 companies certified as a 2025 Global Top Employer and the first and only semiconductor company to achieve this distinction. ST was recognized in this ranking thanks to its continuous improvement approach and stands out particularly in the areas of ethics & integrity, purpose & values, organization & change, business strategy, and performance.
At ST, we endeavor to foster a diverse and inclusive workplace, and we do not tolerate discrimination. We aim to recruit and retain a diverse workforce that reflects the societies around us. We strive for equity in career development, career opportunities, and equal remuneration. We encourage candidates who may not meet every single requirement to apply, as we appreciate diverse perspectives and provide opportunities for growth and learning. Diversity, equity, and inclusion (DEI) is woven into our company culture.
To discover more, visit st.com/careers.

Work arrangement
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