RISC-V NPU Architect

This role will be based out of Dubai and organization will sponsor the relocation
As a RISC-V Architect, you will own the architecture of our AI Accelerator — a many-core RISC-V compute cluster. You will define the base ISA, the vector and matrix extensions, the per-core microarchitecture, and the cluster/NoC topology that turn real AI training and inference workloads into synthesizable, verification-ready RTL feeding our next-generation silicon. You set the architectural contracts that RTL, verification, toolchain, and compiler teams build against, and drive the integration and microarchitecture reviews that keep silicon faithful to the spec.
Responsibilities
As a RISC-V Architect, you will own the architecture of our AI Accelerator — a many-core RISC-V compute cluster. You will define the base ISA, the vector and matrix extensions, the per-core microarchitecture, and the cluster/NoC topology that turn real AI training and inference workloads into synthesizable, verification-ready RTL feeding our next-generation silicon. You set the architectural contracts that RTL, verification, toolchain, and compiler teams build against, and drive the integration and microarchitecture reviews that keep silicon faithful to the spec.

Work arrangement
Yes