Lead RTL Engineer

Requirements:
12+ years of RTL design experience in SystemVerilog.
At least 1 tapeout through to GDSII (not just RTL you've seen the full flow).
Synthesis and timing closure experience (Design Compiler or Genus, PrimeTime or Tempus) Processor, DSP, or datapath-heavy design experience.
Familiarity with advanced process nodes (28nm class or below).
Strong code review skills: you can spot timing hazards, FSM issues, and non-synthesizable patterns in reviews.
Comfortable leading a small team while remaining hands-on.
Nice to Have
VLIW or vector processor design experience.
Experience with deterministic/real-time architectures (no caches, fixed latencies).
Formal verification awareness (writing SVA, working with formal tools).
FPGA prototyping experience (Vivado).

Experience
12-16 yrs