UVM Verification Design Engineer

Job Title: UVM Verification Design Engineer
Location: USA - Remote
Job Type: Contract W2
Must Requirement : End-to-end UVM experience from scratch (across test bench infra development, debug, scoreboard etc.)
Protocol experience like Ethernet, UCIe, PCIe is a plus but it is not mandatory like the end-to-end UVM expertise.
Required Qualifications & Skills:
Experience: 6 to 10+ years of relevant hands-on UVM verification experience in complex digital designs.
Methodologies: Expert-level proficiency in SystemVerilog and UVM, with a proven history of developing testbenches, test sequences, agents, and other components from scratch.
Protocol Knowledge: Hands-on verification experience with one or more high-speed protocols:
UCIe (Universal Chiplet Interconnect Express) 2.0
PCIe (Gen 4/5/6)
Ethernet (MAC/PCS/PMA layers)
Domain Background: Proven track record working on complex networking silicon, Switches, NICs, or high-performance interconnect ASICs.
Debugging Skills: Strong expertise in waveform analysis, protocol debugging, root-cause analysis, and regression triage using simulators (Synopsys VCS, Cadence Xcelium, or Mentor Questa).
Soft Skills: Strong problem-solving abilities, solid communication skills, and the capability to work autonomously in a collaborative, customer-facing environment.

Work arrangement
No