SOC-Design Verification Engineer 5+ years

Company Description AIonSi is a semiconductor solutions startup delivering VLSI design and verification, automotive functional safety, and AI solutions to global semiconductor clients. Led by seven industry experts, the company focuses on providing end-to-end services for complex SoC designs, including full ownership from concept to tape-out. AIonSi positions itself as a one-stop platform, committed to best-in-class service and uncompromising quality. The team offers deep expertise across IP and SoC design, integration, verification, gate-level simulation (GLS), and physical design, providing a collaborative environment for engineers working on cutting-edge technologies.
Role Description This is a full-time, on-site SOC Design Verification Engineer role based in Hyderabad. The engineer will develop and execute verification plans for complex SoC designs, including testbench architecture, test case development, coverage analysis, and regression management. Daily responsibilities include collaborating with RTL designers and architects to understand specifications, performing functional and formal verification, and debugging failures at block and top level. The role involves writing and reviewing verification documentation, optimizing verification methodologies and flows, and ensuring alignment with project timelines and quality targets. The engineer will also participate in design and verification reviews, support integration and GLS activities, and contribute to continuous improvement of verification processes and tools.
Qualifications
Strong skills in Functional Verification and Debugging, with experience in testbench development, coverage-driven verification, and resolving complex design issues.
Proficiency in RTL Design and Computer Architecture, including understanding of SoC components, bus architectures, memory subsystems, and performance/power trade-offs.
Experience with Formal Verification methodologies and tools, and the ability to integrate formal techniques into the overall verification strategy.
Hands-on experience with industry-standard verification languages and tools (e.g., SystemVerilog/UVM, simulators, waveform viewers, coverage tools).
Familiarity with IP and SoC integration flows, GLS, and collaboration with physical design teams.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
Minimum 5 years of experience in SoC or IP design verification in the semiconductor industry.
Strong analytical and communication skills, with the ability to work effectively in cross-functional teams and mentor junior engineers.

Work arrangement
No