ASIC Design Verification Engineer 4+ years Immediate joiner

Company Description AIonSi is a semiconductor solutions startup delivering VLSI design and verification, automotive functional safety, and AI solutions to global semiconductor clients. Led by seven seasoned industry experts, the company specializes in end-to-end services for complex SoC designs and assumes complete ownership from concept to implementation. AIonSi positions itself as a one-stop platform, committed to best-in-class services without compromising on quality. The team provides comprehensive expertise across IP and SoC design, integration, verification, gate-level simulation (GLS), and physical design, offering engineers exposure to cutting-edge semiconductor projects.
Role Description The ASIC Design Verification Engineer role is a full-time, on-site position based in Bengaluru, focused on verifying complex IP and SoC designs. The engineer will develop verification plans and testbenches, create and execute test cases, and perform functional and formal verification to ensure design correctness. Day-to-day responsibilities include debugging RTL issues, analyzing coverage reports, collaborating with design and architecture teams to clarify specifications, and contributing to continuous improvement of verification methodologies. The role also involves participating in design reviews, documenting verification results, and supporting rapid integration cycles, with an expectation of joining immediately or within a short notice period.
Qualifications
Strong foundation in RTL Design and Computer Architecture, with the ability to understand and review complex digital design implementations.
Hands-on experience in Functional Verification, including testbench development, constrained-random testing, and coverage-driven verification flows.
Practical expertise in Formal Verification techniques and tools, applying them to validate critical blocks and corner-case scenarios.
Advanced Debugging skills for RTL, testbenches, and simulation environments, using waveform analysis and log-based issue isolation.
4+ years of experience in ASIC or SoC design verification, preferably in high-performance or safety-critical domains.
Proficiency with industry-standard EDA tools (e.g., simulators, formal tools, version control) and scripting languages such as Python, Perl, or Shell.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
Strong analytical and communication skills, with the ability to work collaboratively in cross-functional teams and deliver on tight schedules.
Experience with UVM or similar verification methodologies, and familiarity with timing, CDC, and GLS flows is an added advantage.

Work arrangement
No