Senior Design Verification Engineer – UCIe 2.0

Hiring: Senior Design Verification Engineer – UCIe 2.0
Location: Bangalore, India
Experience: 5+ Years
We are looking for an experienced Design Verification Engineer with strong expertise in IP-level verification and hands-on experience with the UCIe 2.0 protocol.
The ideal candidate will have solid experience in SystemVerilog and UVM-based verification methodologies, along with a strong understanding of digital design verification and functional verification environments.
Required Skills & Experience
5+ years of hands-on experience in Design Verification.
Strong experience in IP-level functional verification.
Mandatory hands-on experience with the UCIe 2.0 protocol.
Strong proficiency in SystemVerilog and UVM.
Experience in developing testbenches, test scenarios, and functional coverage.
Good debugging and problem-solving skills.
Good to Have
Experience in subsystem-level verification.
Experience in SoC-level verification and integration.
Familiarity with protocol verification, assertions, and coverage-driven verification methodologies.
Experience working with complex ASIC/IP verification environments.

Work arrangement
No